An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

Author:

Sarkar SantanuORCID,Banerjee Swapna

Publisher

Elsevier BV

Subject

General Engineering

Reference36 articles.

1. A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with signal-independent delta-I noise DfT scheme;Radulov;IEEE Trans. Very Large Scale Integr. Syst.,2014

2. A low cost calibrated DAC for high-resolution video display system;Shen;IEEE Trans. Very Large Scale Integr. Syst.,2012

3. S. Subramanian, H. Hashemi, An 800MSPS quadrature DDFS and integrated nonlinear DAC-filter with <15ns instantaneous frequency hopping time, in: IEEE MTT-S International Microwave Symposium Digest (IMS), 2013, pp. 1–4.

4. A 10-b, 500-MSample/s CMOS DAC in 0.6mm2;Lin;IEEE J. Solid-State Circuits,1998

5. MAX5887, 3.3V, 14-Bit, 500MSPS High Dynamic Performance DAC with Differential LVDS Inputs, 19-2777; Rev 2; 12/03, Maxim Integrated Products, 2003.

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