All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator

Author:

Park Young Jun,Parekh Parth,Yuan Fei

Funder

Natural Science and Engineering Research Council of Canada

Publisher

Elsevier BV

Subject

General Engineering

Reference42 articles.

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2. A precise cyclic CMOS time-to-digital converter with low thermal sensitivity;Chen;IEEE Trans. Nucl. Sci.,2005

3. K-locked-loop and its application in time mode ADC;Guttman,2009

4. Time-mode Circuits for Analog Computations;Ravinuthula,2006

5. Anti-imaging time-mode filter design using a PLL structure with transfer function DFT;Aouini;IEEE Trans. Circ. Syst. I,2012

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1. Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter;Microelectronics Journal;2022-01

2. Performance evaluation of measured time stretching approach for event timer;2021 IEEE 9th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE);2021-11-25

3. Time‐to‐digital converters—A comprehensive review;International Journal of Circuit Theory and Applications;2021-01-18

4. All‐digital power‐efficient integrating frequency difference‐to‐digital converter for GHz frequency‐locking;IET Circuits, Devices & Systems;2020-11

5. All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line;2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS);2020-08

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