1. Reliability of dual damascene TSV for high density integration: the electromigration issue;Moreau,2013
2. Effect of post-chemical–mechanical polishing surface treatments on the interfacial adhesion energy between Cu and a capping layer;Kim;Jpn. J. Appl. Phys.,2013
3. Optimization of via bottom cleaning for bumpless interconnects and wafer-on-wafer (WOW) integration;Kim,2018
4. Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: from transistors to packages;Son,2013
5. Pixel/DRAM/logic 3-layer Stacked CMOS image sensor technology;Tsugawa,2017