Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL

Author:

WANG Hui,CHEN Ying-mei,YI Lv-fan,WEN Guan-guo

Publisher

Elsevier BV

Subject

Computer Networks and Communications,Information Systems,Signal Processing

Reference8 articles.

1. Frequency agile jitter measurement system. Application Note 1267,2005

2. Design of integrated circuits for optical communications;Razavi,2003

3. SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application;Greshishchev;IEEE Journal of Solid-State Circuits,2000

4. ITU-T G.8251. The control of jitter and wander within the optical transport network. 2001.

5. A 155-MHz clock recovery delay-and phase-locked loop;Lee;IEEE Journal of Solid-State Circuits,1992

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1. The shale gas revolution in China—problems and countermeasures;Earth Sciences Research Journal;2018-07-01

2. Effect of Random Jitter on Performance of LDPC;Applied Mechanics and Materials;2013-08-30

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