Development of FPGA based phase alignment logic for the high speed protocol in HEP Experiments-Reference-Cited by-同舟云学术

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Development of FPGA based phase alignment logic for the high speed protocol in HEP Experiments

Published:2021-02 Issue: Volume:259 Page:107649
ISSN:0010-4655
Container-title:Computer Physics Communications
language:en
Short-container-title:Computer Physics Communications

Author:

Khan Shuaib Ahmad,Mitra Jubin,Nayak Tapan K.

Funder

CPPM

Publisher

Elsevier BV

Subject

General Physics and Astronomy,Hardware and Architecture

Reference25 articles.

1. Upgrade of the ALICE Readout and Trigger System;Antonioli,2013

2. Trigger and timing distributions using the TTC-PON and GBT bridge connection in ALICE for the LHC Run 3 Upgrade

3. The ALICE DAQ: current status and future challenges

4. GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

5. 2015 Design, Automation Test in Europe Conference Exhibition (DATE);Mamaghani,2015

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. FPGA Based High Speed DAQ Systems for HEP Experiments: Potential Challenges;Advanced Radiation Detector and Instrumentation in Nuclear and Particle Physics;2023

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