Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture-Reference-Cited by-同舟云学术

Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture

Published:2014-06 Issue:6 Volume:74 Page:2452-2460
ISSN:0743-7315
Container-title:Journal of Parallel and Distributed Computing
language:en
Short-container-title:Journal of Parallel and Distributed Computing

Author:

Nukala Nishant S.,Kulkarni Niranjan,Vrudhula Sarma

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference15 articles.

1. Spin-transfer torque MRAMS for low power memories: Perspective and prospective;Augustine;IEEE Sensors Journal,2012

2. VLSI implementations of threshold logic — a comprehensive survey;Beiu;IEEE Transactions on Neural Networks,2003

3. E. Blair, C. Lent, Quantum-Dot cellular automata: an architecture for molecular computing, in: International Conference on Simulation of Semiconductor Processes and Devices, 2003, SISPAD 2003, Sep 2003, pp. 14–18.

4. EETimes: The future of scalable STT-RAM as a universal embedded memory. http://www.eetimes.com/design/embedded/4026000/The-future-of-scalable-STT-RAM-as-a-universal-embedded-memory.

5. A high-reliability, low-power magnetic full adder;Gang;IEEE Transactions on Magnetics,2011

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing Elements;ACM Transactions on Embedded Computing Systems;2022-11-30

2. Constraint Solving for Synthesis and Verification of Threshold Logic Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-05

3. Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks;2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD);2019-11

4. Practical Implementation of Memristor-Based Threshold Logic Gates;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-08

5. Canonicalization of threshold logic representation and its applications;Proceedings of the International Conference on Computer-Aided Design;2018-11-05