Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study

Author:

Tuzov Ilya,de Andrés DavidORCID,Ruiz Juan-Carlos

Funder

Ministerio de Economía, Industria y Competitividad de España

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference34 articles.

1. Altera Corp., Quartus Prime Pro Edition Handbook Volume 2: Design Implementation and Optimization, 2015. URL https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qpp-5v2.pdf.

2. VHDL simulation-based fault injection techniques;Gil,2003

3. Statistics for Experimenters: Design, Innovation, and Discovery;Box,2005

4. Cobham Gaisler AB, LEON3 processor product sheet, 2016. URL http://www.gaisler.com/doc/leon3_product_sheet.pdf.

5. Design and Modeling for Computer Experiments;Fang,2005

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2. Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology;Journal of Parallel and Distributed Computing;2019-11

3. Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection;2018 Eighth Latin-American Symposium on Dependable Computing (LADC);2018-10

4. Analyzing the Influence of LLVM Code Optimization Passes on Software Performance;Communications in Computer and Information Science;2018

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