Implementing sequentially consistent programs on processor consistent platforms-Reference-Cited by-同舟云学术

Implementing sequentially consistent programs on processor consistent platforms

Published:2008-04 Issue:4 Volume:68 Page:488-500
ISSN:0743-7315
Container-title:Journal of Parallel and Distributed Computing
language:en
Short-container-title:Journal of Parallel and Distributed Computing

Author:

Higham Lisa,Kawash Jalal

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference41 articles.

1. S. Adve, Using information from the programmer to implement system optimizations without violating sequential consistency, Technical Report ECE 9603, Department of Electrical and Computer Engineering, Rice University, June 1998.

2. S. Adve, K. Gharachorloo, A. Gupta, J. Hennessy, M. Hill, Sufficient system requirements for supporting the PLpc memory model, Technical Report 1200 (or CSL-TR-93-595), University of Wisconsin-Madison (or Stanford University), 1993.

3. S. Adve, M. Hill, Weak ordering—a new definition, in: Proceedings of the 17th International Symposium on Computer Architecture, May 1990, pp. 2–14.

4. S. Adve, M. Hill, Sufficient conditions for implementing data-race-free-1 memory model, Technical Report 1107, University of Wisconsin-Madison, 1992.

5. A unified formalization of four shared-memory models;Adve;IEEE Trans. Parallel Distributed Systems,1993

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