Author:
Pal Rajesh Kumar,Paul Kolin,Prasad Sanjiva
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software
Reference51 articles.
1. A workload-adaptive and reconfigurable bus architecture for multicore processors;Akram;Int. J. Reconfig. Comput.,2010
2. D.H. Albonesi, Selective cache ways: on-demand cache resource allocation, in: Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, pp. 248–259.
3. Dynamically tuning processor resources with adaptive processing;Albonesi;Trans. Comput.,2003
4. A. Avakian, J. Nafziger, A. Panda, R. Vemuri, A reconfigurable architecture for multicore systems, in: IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum, 2010, pp. 1–8.
5. R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas, Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures, in: Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, 2000, pp. 245–257.
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