1. Multiple si layer ics: motivation, performance analysis, and design implications;Souri,2000
2. A global interconnect design window for a three-dimensional system-on-a chip;Joyner,2001
3. International Technology Roadmap for Semiconductors (http://public.itrs.net/home.html)
4. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits;Zhou,2007
5. Fixed-outline floorplanning: enabling hierarchical design;Adya;IEEE Trans. Very Large Scale Integr. Syst.,2003