An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip-Reference-Cited by-同舟云学术

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An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip

Published:2016-10 Issue: Volume:55 Page:112-122
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Wiersema Tobias,Bockhorn Arne,Platzner Marco

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference19 articles.

1. Embedding FPGA overlays into configurable systems-on-chip: ReconOS meets ZUMA;Wiersema,2014

2. ZUMA: An open FPGA overlay architecture;Brant,2012

3. ReconOS: An operating system approach for reconfigurable computing;Agne;IEEE Micro,2013

4. ReconOS: Multithreaded programming for reconfigurable computers;Lübbers;ACM Trans Embedded Comput Syst,2009

5. The swappable logic unit: A paradigm for virtual hardware;Brebner,1997

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Timing Optimization for Virtual FPGA Configurations;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2021

2. ROUTING RESOURCES REDUCTION OF VIRTUAL FPGA FOR SPECIFIC APPLICATION SETS;INT J INNOV COMPUT I;2020

3. Hardware implementation of fault tolerance NoC core mapping;Telecommunication Systems;2017-12-11

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