A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

Author:

García Rommel,Algredo-Badillo Ignacio,Morales-Sandoval Miguel,Feregrino-Uribe Claudia,Cumplido René

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference22 articles.

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2. Reddy SK, Sakthivel R, Praneet P. VLSI implementation of AES crypto processor for high throughput. In: (IJAEST) International journal of advanced engineering sciences and technologies, vol. 6; 2011. p. 022–6.

3. Managing security in FPGA-based embedded systems;Huffmire;IEEE Des Test Comput,2008

4. Crenne J, Cotret P, Gogniat G, Tessier R, Diguet J-P. Efficient key-dependent message authentication in reconfigurable hardware. In: 2011 International conference on field-programmable technology (FPT’11); 2011. p. 1–6.

5. National Technical Information Service. FIPS 180-2 – secure hash standard, U.S. Department of Commerce/NIST, Springfield, VA; 2002 .

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