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An assertion-based verification methodology for system-level design

  • Published:2007-07 Issue:4 Volume:33 Page:269-284
  • ISSN:0045-7906
  • Container-title:Computers & Electrical Engineering
  • language:en
  • Short-container-title:Computers & Electrical Engineering

Author:

Gharehbaghi Amir Masoud,Yaran Benyamin Hamdin,Hessabi Shaahin,Goudarzi Maziar

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference21 articles.

1. Goudarzi M, Hessabi S, Mycroft A. Object-oriented ASIP design and synthesis. Forum on Design & Specification Languages (FDL), Sep. 2003.

2. Property Specification Language 1.01 LRM, www.accellera.org.

3. SystemVerilog 3.1 LRM, www.accellera.org.

4. Combining system level modeling with assertion based verification;Dahan;Int Symp Quality Electron Design (ISQED),2005

5. Efficient generation of monitor circuits for GSTE assertion graphs;Hu;Int Conf Comput-Aided Des (ICCAD),2003

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