User satisfaction aware routing and energy modeling of polymorphic network on chip architecture-Reference-Cited by-同舟云学术

User satisfaction aware routing and energy modeling of polymorphic network on chip architecture

Published:2014-11 Issue:8 Volume:40 Page:260-275
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Ponpandi Swamy D.,Tyagi Akhilesh

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference19 articles.

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2. Krishnamurthy V, Ponpandi SD, Tyagi A. A novel thread scheduler design for polymorphic embedded systems. In: Proceedings of the 14th international conference on compilers, architectures and synthesis for embedded systems (CASES); 2011. p. 75–84.

3. Dally W, Towles B. Route packets, not wires: on-chip interconnection networks. In: Proceedings of design automation conference (DAC); 2001. p. 684–9.

4. A survey of research and practices of network-on-chip;Bjerregaard;ACM Comput Surv,2006

5. Virtual channel flow control;Dally;IEEE Trans Parallel Distrib Syst,1992

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