1. “Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders”;Neeb,2005
2. Network-on-Chip design and synthesis outlook”;David Atienzaa;Integration, the VLSI journal Elsevier,2008
3. Dr. Rosula S.J. Reyes, Carlos M. Oppus, Jose Claro N. Monje, Noel S. Patron, Reynaldo C. Guerrero, JovilynTherese B. Fajardo “FPGA Implementation of a Telecommunications Trainer System” International Journals of Circuits, Systems and Signal processing, 1-9.
4. QNoC: QoS architecture and design process for network on chip;Bolotin;Journal of Systems Architecture,2004
5. John. C. Bellamy, Reprint 2011” Digital Switching, Chapter 5 pp 225-245” Digital Telehony, Wiley India Pvt. Ltd, India.