Architectural Level Crosstalk Minimization: A Tool
Author:
Publisher
Elsevier BV
Subject
General Engineering
Reference21 articles.
1. A post processing algorithm for crosstalk- driven wire perturbation;Saxena Van;IEEE Trans.on Computer-Aided Design of. Integrated Circuits and Systems,vol.,2000
2. N. Hanchate and N. Ranganathan, “A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk. noise,” in proc. Intl. Conf.on VLSI Design, 2006.
3. Simultaneous interconnect delay and crosstalk noise optimization. through gate sizing using game theory;Hanchate;IEEE Trans. Computers,2006
4. ” Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing;Jiang;IEEE Trans. Computer. Aided Design of IntegratedCircuits and Systems,2000
5. An optimal layer assignment algorithm for minimizing crosstalk for three layer VHV channel. routing;Thakur;in proc. ISCAS,1995
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1. Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis;E3S Web of Conferences;2024
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