Area Efficient Complex Floating Point Multiplier for Reconfigurable FFT/IFFT Processor Based on Vedic Algorithm

Author:

Thakare L.P.,Deshmukh A.Y.

Publisher

Elsevier BV

Subject

General Engineering

Reference10 articles.

1. KamarajuDesign of high performance IEEE-754 single precision (32 bit) floating point adder using VHDL;Preethi sudha Gollamudi;IJERT,2013

2. IEEE standard for floating-point arithmetic(IEEE STD 754-2008),revision of IEEE std 754-1985.august (2008).

3. Loucas Louca, Todd A cook and William H. Johnson, “Implementation of IEEE single precision floating point addition and multiplication on FPGAs,”©1996 IEEE.

4. Ali malik, Soek bum ko, “Effective implementation of floating point adder using pipelined LOP in FPGAss,” ©2010 IEEE.

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder;International Journal of Electronics;2023-11-06

2. Design of 64-bit Floating-Point Arithmetic and Logical Complex Operation for High-Speed Processing;2023 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE);2023-01-27

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