High throughput and energy efficient FIR filter architectures using retiming and two level pipelining-Reference-Cited by-同舟云学术

High throughput and energy efficient FIR filter architectures using retiming and two level pipelining

Published:2020 Issue: Volume:171 Page:617-626
ISSN:1877-0509
Container-title:Procedia Computer Science
language:en
Short-container-title:Procedia Computer Science

Author:

Patali Pramod,Kassim Shahana Thottathikkulam

Publisher

Elsevier BV

Subject

General Engineering

Reference28 articles.

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3. VLSI Digital Signal Processing Systems Design and implementation;Parhi,2007

4. New hardware-efficient architecture for programmable FIR filter;Lee;IEEE Trans. Circuits Sys.,1996

5. K. Azadet and C.K. Nicole, (1998) "Low-power equalizer architectures for high-speed modems," IEEE Comm. Mag.

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