Author:
Patali Pramod,Kassim Shahana Thottathikkulam
Reference28 articles.
1. S.Carlo, and O. Tokunbo,(2015) "FPGA implementation of LMS-based FIR adaptive filter for Real time Digital Signal Processing Applications". Proc. IEEE International Conf. Digital Signal Processing.
2. N.S. Johannes and L. Boris/REFAU>, (2017) "Optimal feedforward preview control by FIR filters," IFAC Papers OnLine5115–5120.
3. VLSI Digital Signal Processing Systems Design and implementation;Parhi,2007
4. New hardware-efficient architecture for programmable FIR filter;Lee;IEEE Trans. Circuits Sys.,1996
5. K. Azadet and C.K. Nicole, (1998) "Low-power equalizer architectures for high-speed modems," IEEE Comm. Mag.
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