Improvement in the speed of FFT processors using segmented memory and parallel arithmetic units-Reference-Cited by-同舟云学术

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Improvement in the speed of FFT processors using segmented memory and parallel arithmetic units

Published:1985-04 Issue:2 Volume:8 Page:267-274
ISSN:0165-1684
Container-title:Signal Processing
language:en
Short-container-title:Signal Processing

Author:

Sinha Bhabani P.,Dattagupta Jayasree,Sen Asish

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Signal Processing,Software,Control and Systems Engineering

Reference4 articles.

1. An algorithm for the machine calculation of complex Fourier Series;Cooley;Math. Comp.,1965

2. Fast Fourier transform hardware implementations — An overview;Bergland;IEEE Trans. Audio Electroacoust.,1969

3. Hardware modifications in radix-2 cascade FFT processors;Agarwal;IEEE Trans. Acoust. Speech, Signal Processing,1978

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Real-Time FFT Computation Using GPGPU for OFDM-Based Systems;Circuits, Systems, and Signal Processing;2015-06-20

2. Partial column FFT pipelines;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;1995-06

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