Input compression and efficient VLSI architectures for rank order and stack filters-Reference-Cited by-同舟云学术

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Input compression and efficient VLSI architectures for rank order and stack filters

Published:1994-08 Issue:3 Volume:38 Page:441-453
ISSN:0165-1684
Container-title:Signal Processing
language:en
Short-container-title:Signal Processing

Author:

Adams George B,Coyle Edward J,Lin Liangchien,Lucke Lori E,Parhi Keshab K

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Signal Processing,Software,Control and Systems Engineering

Reference37 articles.

1. A median filter architecture suitable for VLSI implementation;Arce,1984

2. Sorting networks and their applications;Batcher,1968

3. Recursive algorithms and VLSI implementations for median filtering;Boncelet,1988

4. The weighted median filter;Brownrigg;Commun. Assoc. Comput. Mach.,1984

5. High sample rate systolic architectures for median filters;Chakrabarti,1992

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1. The realisation of selected signal processing functions by means of stack filters;B POL ACAD SCI-TECH;2018

2. Immune memory clonal selection algorithms for designing stack filters;Neurocomputing;2007-01

3. Pass-transistor based implementations of threshold logic gates for WOS filtering;Microelectronics Journal;2004-11

4. A Practical Parallel Architecture for Stacks Filters;The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology;2004-09

5. Weighted order statistics filter for real-time signal processing applications based on pass transistor logic;IEE Proceedings - Circuits, Devices and Systems;2004

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