Dynamic malfunction limits in high-speed TTL and ECL integrated digital gates-Reference-Cited by-同舟云学术

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Dynamic malfunction limits in high-speed TTL and ECL integrated digital gates

Published:1973-02 Issue:1 Volume:12 Page:57-58
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Abdel-Latif M.,Strutt M.J.O.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference6 articles.

1. Simple graphical method to determine line reflections between high-speed logic integrated circuits;Abdel-Latif;Electron. Lett.,1968

2. Interconnection and noise immunity of circuitry in digital computers;Yao;IEEE Trans. Electron. Comput.,1965

3. The effects of interconnections on high-speed logic circuits;Jarvis;IEEE Trans. Electron. Comput.,1963

4. Theoretical and experimental analysis of crosstalk in line connected pulsed digital circuits;Abdel-Latif;Archiv Elek. Uebertr.,1971

5. Impairment of noise immunity of digital monolithic integrated circuits caused by supply-line and earth-line current spikes in conjunction with coaxial-cable connections;Abdel-Latif;Electron. Lett.,1970

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