Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering-Reference-Cited by-同舟云学术

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Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Published:1995-05 Issue:5 Volume:35 Page:821-826
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Andhare P.N.,Nahar R.K.,Chandra S.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. Enhanced performance 4K × 1 high speed SRAM using optically defined sub-micrometer devices in selected circuits;Chatterjee;IEEE Trans.,1982

2. Deep submicrometer MOS device fabrication using a photoresist ashing technique;Chung;IEEE Electron Device Lett.,1988

3. VLSI Limitation from Drain Induced Barrier Lowering;Troutman;IEEE Trans. Electron Devices,1979

4. Deep implant 1 μm MOSFET structure with improved threshold control for VLSI Circuitry;Risch;IEEE Trans. Electron Devices,1982

5. Electrical characteristics of a DSA MOS Transistor with a fine structure;Okhura;IEEE Trans. Electron Devices,1979

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