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An extended dual input dual output three level Z source inverter with improved switch loss reduction technique

  • Published:2016-12 Issue:3 Volume:3 Page:398-410
  • ISSN:2314-7172
  • Container-title:Journal of Electrical Systems and Information Technology
  • language:en
  • Short-container-title:Journal of Electrical Systems and Information Technology

Author:

Deshmukh N.B.,Thombare R.D.,Waware M.M.,More D.S.

Publisher

Springer Science and Business Media LLC

Subject

General Medicine

Reference14 articles.

1. Reduced switching loss pulse width modulation technique for three-level diode clamped inverter;Chaturvedi;IET Power Electron.,2011

2. Carrier-based neutral point potential regulator with reduced switching losses for three-level diodeclamped inverter;Chaturvedi;IEEE Trans. Ind. Electron.,2014

3. A dual-input–dual-output Z-source inverter;Dehghan;IEEE Trans. Power Electron.,2010

4. A novel three level inverter which can drive two PMSMs;Haruna,2014

5. Switching loss minimized space vector PWM method for IGBT three-level inverter;Kaku;IEE Proc. Electr. Power Appl.,1997

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Modified Z Source Grid Tied Inverter System;International Journal of Electrical and Electronics Research;2022-12-30

2. Design of a Novel Dual-Output Multilevel PWM Converter;2022 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES);2022-12-14

3. A Three-level Neutral-Point Clamped Dual-Output Converter;2021 IEEE Energy Conversion Congress and Exposition (ECCE);2021-10-10

4. Design and Analysis of Dual Output Three Level Inverter with Reduced Switch Count Topology;IETE Journal of Research;2020-11-09
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