1. Modeling MOS VLSI circuits for transient analysis;Subramaniam;IEEE J. Solid State Circuits,1986
2. Macromodeling and optimization of digital MOS VLSI circuits;Matson;IEEE Trans. CAD,1986
3. A timing model for static CMOS gates;Chen,1989
4. Polynomial delay models for optimization-based transistor sizing in digital CMOS VLSI circuits;Hoppe,1989
5. An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation;Jun;IEEE Trans. CAD,1989