Hardware information flow tracking based on lightweight path awareness

Author:

Sun Haodong,Yang ZhiORCID,Chen Xingyuan,Xu Hang,Yuan ZhanhuiORCID

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Reference20 articles.

1. Aciiçmez, Onur, 2007. Yet another microarchitectural attack: exploiting I-cache. In: Proceedings of the 2007 ACM Workshop on Computer Security Architecture. pp. 11–18.

2. Aciiçmez, Onur, Koç, Çetin Kaya, Seifert, Jean-Pierre, 2007. On the power of simple branch prediction analysis. In: Proceedings of the 2nd ACM Symposium on Information, Computer and Communications Security. pp. 312–320.

3. Register transfer level information flow tracking for provably secure hardware design;Ardeshiricham,2017

4. Cadence,, 2024. Jasper Security Path Verification App, https://www.cadence.com/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform/security-path-verification-app.html.

5. Secchisel: Language and tool for practical and scalable security verification of security-aware hardware architectures;Deng,2017

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