A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in holding current prediction
Author:
Publisher
Elsevier BV
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference18 articles.
1. Latch-Up in CMOS Integrated Circuits
2. The Physics and Modeling of Latch-up and CMOS Integrated Circuits;Estreich,1980
3. Prevention of CMOS Latch-Up by Gold Doping
4. Neutron Irradiation for Prevention of Latch-Up in MOS Integrated Circuits
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Simultaneous optimization and simulation of a-Si1−xCx layers on n-type silicon solar cells;Solar Energy Materials and Solar Cells;2005-02
2. Correlations between CMOS latch-up characteristics and substrate structure parameters;Solid-State Electronics;1986-10
3. An efficient method for calculating the d.c. triggering currents in CMOS latch-up;Solid-State Electronics;1986-05
4. An efficient two-dimensional model for CMOS latchup analysis;Solid-State Electronics;1986-04
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