A generalized algorithm for CMOS circuit delay, power, and area optimization

Author:

Lai F.S.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers;IEEE Transactions on Circuits and Systems II: Express Briefs;2008-01

2. Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers;2007 IEEE International Symposium on Circuits and Systems;2007-05

3. Integrated Circuit Signal Delay;Wiley Encyclopedia of Electrical and Electronics Engineering;1999-12-27

4. Transistor transient studies including transcapacitive current and distributive gate resistance for inverter circuits;IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications;1998-04

5. Effects of simultaneous switching noise on the tapered buffer design;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;1997-09

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