1. 3D packaging for heterogeneous integration;Agarwal,2022
2. Future logic scaling: Towards atomic channels and deconstructed chips;Samavedam;IEEE Int. Electron. Meet. (IEDM),2020
3. Wafer to wafer bonding to increase memory density;Yolanda,2022
4. Next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications;Cheng;IEEE Int. Electron. Meet. (IEDM),2020
5. System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs;Perumkunnil;IEEE Int. Electron. Meet. (IEDM),2020