Facilitating the design of fault tolerance in transaction level SystemC programs-Reference-Cited by-同舟云学术

Facilitating the design of fault tolerance in transaction level SystemC programs

Published:2013-07 Issue: Volume:496 Page:50-68
ISSN:0304-3975
Container-title:Theoretical Computer Science
language:en
Short-container-title:Theoretical Computer Science

Author:

Ebnenasir Ali,Hajisheykhi Reza,Kulkarni Sandeep S.

Publisher

Elsevier BV

Subject

General Computer Science,Theoretical Computer Science

Reference31 articles.

1. Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench;Thomas,1989

2. Y.-Y. Chen, C.-H. Hsu, K.-L. Leu, SoC-level risk assessment using FMEA approach in system design with SystemC, in: International Symposium on Industrial Embedded Systems, 2009, pp. 82–89.

3. Open SystemC Initiative (OSCI): Defining and advancing SystemC standard IEEE 1666–2005. http://www.systemc.org/.

4. Transaction-Level Modeling (TLM) 2.0 Reference Manual. http://www.systemc.org/downloads/standards/.

5. A. Fin, F. Fummi, M. Martignano, M. Signoretto, SystemC: A homogenous environment to test embedded systems, in: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES’01, 2001, pp. 17–22.

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