A new cache architecture based on temporal and spatial locality

Author:

Lee Jung-Hoon,Lee Jang-Soo,Kim Shin-Dug

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference19 articles.

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2. C. Su, A. Despain, Cache design tradeoffs for power and performance optimization: A case study, ACM/IEEE International Symposium on Low-Power Design, Dana Point, CA (1996) 63-68

3. J. Kin, M. Gupta, W.H. Mangione-Smith, The filter cache: An energy efficient memory structure, MICRO-97: ACM/IEEE International Symposium on Microarchitecture, Research Triangle Park, NC (1997) 184–193

4. Samsung Electronics, ASIC MDL110 Data Book: 0.25 μm 2.5V CMOS Standard Cell Library for Pure Logic/MDL products (1999) 5-32 5-44

5. The split temporal/spatial cache: Initial performance analysis;Milutinovic;SCIzzL-5,1996

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