Funder
Electronics and Communication Department
Reference21 articles.
1. A. Agal, Pardeep, B. Krishan, 6T SRAM Cell: Design And Analysis, Int. J. Eng. Res. Appl. 4 (2014) 574–577.
2. A. Bhaskar, Design and analysis of low power SRAM cells, in: 2017 Innovations in Power and Advanced Computing Technologies (I-PACT), IEEE, 2017: pp. 1–5. doi:10.1109/IPACT.2017.8244888.
3. Y. Cao, A. Balijepalli, S. Sinha, C.-C. Wang, W. Wang, W. Zhao, The Predictive Technology Model in the Late Silicon Era and Beyond, Foundations and Trends® in Electronic Design Automation. 3 (2009) 305–401. doi:10.1561/1000000012.
4. M. Jagasivamani, Dong Sam Ha, “Development of a low-power SRAM compiler,”ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), Sydney, NSW, 2001, pp. 498-501 vol. 4.
5. P.S. Kanhaiya, C. Lau, G. Hills, M. Bishop, M.M. Shulaker, 1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS, in: 2019 Symposium on VLSI Technology, IEEE, 2019: pp. T54–T55. doi:10.23919/VLSIT.2019.8776563.
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献