An energy efficient high-speed quantum-dot based full adder design and parity gate for nano application-Reference-Cited by-同舟云学术

An energy efficient high-speed quantum-dot based full adder design and parity gate for nano application

Published:2022 Issue: Volume:62 Page:4880-4890
ISSN:2214-7853
Container-title:Materials Today: Proceedings
language:en
Short-container-title:Materials Today: Proceedings

Author:

Patidar Mukesh,Shrivastava Anurag,Miah Shahajan,Kumar Yogendra,Sivaraman Arun Kumar

Publisher

Elsevier BV

Subject

General Medicine

Reference36 articles.

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2. Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology;Patidar;J. Supercomput.,2021

3. Design of a practical fault-tolerant adder in QCA;Kumar;Elsevier Microelectron. J.,2016

4. Basic Reversible Logic Gates and It’s QCA Implementation;Biswas;Int. J. Eng. Res. Appl.,2014

5. Design of efficient and testable n-input logic gates in quantum-dot cellular automata;Sayedsalehi;Am. Sci. Publ., J. Comput. Theoretical Nano Sci.,2013

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