An efficient VLSI architecture for CBAC of AVS HDTV decoder-Reference-Cited by-同舟云学术

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An efficient VLSI architecture for CBAC of AVS HDTV decoder

Published:2009-04 Issue:4 Volume:24 Page:324-332
ISSN:0923-5965
Container-title:Signal Processing: Image Communication
language:en
Short-container-title:Signal Processing: Image Communication

Author:

Zheng Junhao,Gao Wen,Wu David,Xie Don

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Signal Processing,Software

Reference15 articles.

1. AVS working group official website, 〈http://www.avs.org.cn〉.

2. AVS-Group, Information Technology—Advanced Coding of Audio and Video—Part 2: Video, AVS1-P2, 2005.

3. AVS-Group, Information Technology—Advanced coding of audio and video—Part 2: Video, AVS-X CD 5.0, 2008.

4. J. Zhou, L. Xiong, Coding Efficiency Comparison: AVS-P2 Jizhun Profile, X Profile, and H.264 High Profile (AVS_M1989), AVS video proposal, 2007.

5. ITU-T, Advanced Video Coding for Generic Audio Visual Services, ITU-T Recommendation H.264 | ISO/IEC 14496-10 (MPEG-4 AVC), 2005.

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1. High Throughput CBAC Hardware Encoder With Bin Merging for AVS 2.0 Video Coding;IEEE Transactions on Circuits and Systems for Video Technology;2021-11

2. FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach;International Journal of Reconfigurable Computing;2019-04-01

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