Empirical models of miss rates-Reference-Cited by-同舟云学术

Empirical models of miss rates

Published:1998-02 Issue:2 Volume:24 Page:205-219
ISSN:0167-8191
Container-title:Parallel Computing
language:en
Short-container-title:Parallel Computing

Author:

Lee Kangwoo,Dubois Michel

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference13 articles.

1. V.A. Aho, J.E. Hopcroft, J.D. Ullman, Data Structures and Algorithms, Addison-Wesley Publishing Company, 1983.

2. M. Brorsson, F. Dahlgren, H. Nilsson, P. Stenstrom, The CacheMire test bench – A flexible and effective approach for simulation of multiprocessors, in: Proc. of 26th Ann. IEEE International Simulation Symposium, April 1993, pp. 41–49.

3. M. Dubois, F.A. Briggs, Effects of cache coherency in multiprocessors, in: Proc. of 9th Ann. International Symposium on Computer Architecture, May 1982, pp. 299–308.

4. M. Dubois, J.C. Wang, Shared block contention in a cache coherence protocol, IEEE Transactions on Computers 40 (5) (1991).

5. M. Dubois, J. Skeppstedt, L. Ricciulli, K. Ramamurthy, P. Stenstrom, Detection and elimination of useless misses in multiprocessors, in: Proc. of 20th Ann. International Symposium on Computer Architecture, May 1993, pp. 88–97.

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