Efficient implementation of regular parallel adders for binary signed digit number representations-Reference-Cited by-同舟云学术

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Efficient implementation of regular parallel adders for binary signed digit number representations

Published:1992-09 Issue:1-5 Volume:35 Page:319-326
ISSN:0165-6074
Container-title:Microprocessing and Microprogramming
language:en
Short-container-title:Microprocessing and Microprogramming

Author:

Zehendner Eberhard

Publisher

Elsevier BV

Subject

General Engineering

Reference13 articles.

1. Extreme Area-Time Tradeoffs in VLSI;Sugla;IEEE Transactions on Computers,1990

2. On-line Arithmetic: an Overview;Ercegovac;SPIE, Vol. 495, Real Time Signal Processing VII,1984

3. Ecrine les nombres autrement pour calculer plus vite;Duprat;Technique et Science Informatiques,1991

4. Signed-Digit Number Representations for Fast Parallel Arithmetic;Avizienis;IRE Transactions on Electronic Computers,1961

5. Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations;Parhami;IEEE Transactions on Computers,1990

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. QCA-Based Adder for Redundant Binary Signed Digit Numbers;Arabian Journal for Science and Engineering;2022-02-16

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