Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation-Reference-Cited by-同舟云学术

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Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation

Published:1991-08 Issue:1-5 Volume:32 Page:75-82
ISSN:0165-6074
Container-title:Microprocessing and Microprogramming
language:en
Short-container-title:Microprocessing and Microprogramming

Author:

Eshraghian K.,Sarmiento R.,Carballo P.P.,Núñez A.

Publisher

Elsevier BV

Subject

General Engineering

Reference4 articles.

1. Fundamentals of High Speed Systems: Gallium Arsenide VLSI Technology;Eshraghian,1991

2. The application of Gallium Arsenide Integrated Circuit Technology to the Design and Fabrication of Future Generation Digital Signal Processors: Problems and Promises;Gilbert,1987

3. A 6.5-ns GaAs 20x20-b Parallel Multiplier with 67-ps Gate Delay;Singh;IEEE Journal of Solid-State Circuits,1990

4. A Regular Layout for Parallel Adders;Brent;IEEE Transactions on Computers,1983

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2. Gallium arsenide processing elements for motion estimation full-search algorithm;Electronics and Structures for MEMS II;2001-11-21

3. Low Power Methodologies for GaAs Asynchronous Systems;Mixed Design of Integrated Circuits and Systems;1998

4. Efficient design of gallium arsenide Muller-C element;Electronics Letters;1997

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