A memory-mapped interprocessor communication architecture using FIFO RAMs-Reference-Cited by-同舟云学术

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A memory-mapped interprocessor communication architecture using FIFO RAMs

Published:1992-02 Issue:1-5 Volume:34 Page:187-191
ISSN:0165-6074
Container-title:Microprocessing and Microprogramming
language:en
Short-container-title:Microprocessing and Microprogramming

Author:

Su Syhy-Chang,Biswas Prasenjit

Publisher

Elsevier BV

Subject

General Engineering

Reference10 articles.

1. A Microprocessor-Based Hypercube Supercomputer;Hayes;IEEE Micro,1986

2. Programming Three Parallel Computers;Kallstrom;IEEE Software,1988

3. A High Speed Message Driven Communication Architecture;Peterson,1988

4. The Post Office Communication Support for Distributed Ensemble Architectures;Stevens,1986

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Data reordering converter: an interface block in a linear chain of processing arrays;Microelectronics Journal;2000-01

2. Development of an innovative, two-processor data processing unit for the magnetospheric imaging instrument onboard the Cassini mission to Saturn. I. Hardware architecture;IEEE Transactions on Geoscience and Remote Sensing;1999-07

3. A transputer based vehicle simulator;Microprocessors and Microsystems;1995-09

4. An optimal scheduling procedure for matrix inversion on linear array at a processor level;International Journal of Parallel Programming;1994-08

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