An analytical model for thread-core mapping for tiled CMPs-Reference-Cited by-同舟云学术

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An analytical model for thread-core mapping for tiled CMPs

Published:2019-10 Issue: Volume:134 Page:102003
ISSN:0166-5316
Container-title:Performance Evaluation
language:en
Short-container-title:Performance Evaluation

Author:

Pranzo Marco,Mazumdar Somnath

Publisher

Elsevier BV

Subject

Computer Networks and Communications,Hardware and Architecture,Modeling and Simulation,Software

Reference47 articles.

1. . Pezy Computing, Pezy Computing Cores. http://pezy.co.jp/en/products/pezy-sc.html.

2. Parallella million cores;Parallella Inc.,2017

3. Principles and Practices of Interconnection Networks;Dally,2004

4. A survey of research and practices of network-on-chip;Bjerregaard;ACM Comput. Surv.,2006

5. Energy and performance benefits of active messages;Harting,2012

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