Author:
Gierenz Volker,Panis Christian,Nurmi Jari
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference49 articles.
1. C. Panis, Scalable DSP core architecture addressing compiler requirements, Ph.D. Thesis, Tampere University of Technology, August 2004.
2. C. Panis, U. Hirnschrott, G. Laure, W. Lazian, J. Nurmi, DSPxPlore: design space exploration methodology for an embedded DSP core, in: Proceedings of the 2004 ACM Symposium on Applied Computing, 2004, pp. 876–883, doi:10.1145/967900.968078.
3. C. Panis, U. Hirnschrott, S. Farfeleder, A. Krall, G. Laure, W. Lazian, J. Nurmi, A scalable embedded DSP core for SoC applications, in: Proceedings of the International Symposium on System-on-Chip, 2004, pp. 85–88, doi:10.1109/ISSOC.2004.1411155.
4. J. Nurmi, S. Leibson, F. Campi, C. Panis, Extensible and configurable processors for system-on-chip design, in: Advanced Signal Processing, Circuits, and System Design Techniques for Communications, 2006, pp. 45–97, doi:10.1109/ASPCAS.2006.251123.
5. Y. Liao, D. Roberts, E. Hoffman, VLSI implementation of a high-performance and low power 32-bit multiply-accumulate unit, in: Proceedings of the 27th European Solid-State Circuits Conference (ESSCIRC 2001), 2001, pp. 269–272.
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