Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding-Reference-Cited by-同舟云学术

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Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding

Published:2014-03 Issue:2 Volume:38 Page:152-169
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Jan Yahya,Jóźwiak Lech

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference38 articles.

1. Modern development methods and tools for embedded reconfigurable systems: a survey;Jóźwiak;Integr. VLSI J.,2010

2. Low-density parity-check codes;Gallager;IRE Trans. Inform. Theory,1962

3. Ieee standard for information technology – telecommunications and information exchange between systems – local and metropolitan area networks – specific requirements. part 15.3: Wireless medium access control (mac) and physical layer (phy) specifications for high rate wireless personal area networks (wpans) amendment 2: Millimeter-wave-based alternative physical layer extension, IEEE Std 802.15.3c-2009 (Amendment to IEEE Std 802.15.3-2003), 2009, pp. c1–187. doi:10.1109/IEEESTD.2009.5284444.

4. G. Lechner, J. Sayir, M. Rupp, Efficient dsp implementation of an ldpc decoder, in: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, (ICASSP ’04), vol. 4, 2004, pp. iv-66 –iv-668. doi:10.1109/ICASSP.2004.1326914.

5. Massively ldpc decoding on multicore architectures;Fernandes;IEEE Trans. Parallel Distribut. Syst.,2011

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1. Advanced mobile and wearable systems;Microprocessors and Microsystems;2017-05

2. Complex Parts Design Based on Macro Programming;Applied Mechanics and Materials;2014-09

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