A design assembly framework for FPGA back-end acceleration-Reference-Cited by-同舟云学术

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A design assembly framework for FPGA back-end acceleration

Published:2014-11 Issue:8 Volume:38 Page:889-898
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Frangieh Tannous,Athanas Peter

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference31 articles.

1. Christoph Albrecht, IWLS 2005 Benchmarks, 2005, .

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5. Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture;Becker;VLSI,2001

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-12

2. Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2018

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