Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology-Reference-Cited by-同舟云学术

Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology

Published:2020-04 Issue: Volume:74 Page:103000
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Nandan V.,Gowri Shankar Rao R.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference22 articles.

1. Smart Card Handbook;Rankl,2009

2. Power-analysis attack on an ASIC AES implementation;Ors;Proc. ITCC,2004

3. Differential power analysis;Kocher,2010

4. A very compact S-box for AES. in: 7th international workshop on cryptographic hardware and embedded systems (CHES);Canright;Lect. Notes Comput. Sci.,2005

5. Design and implementation of low-area and low-power AES encryption hardware core,” proc. 9th euromicro conf. digital system design: architectures;Hamalainen;Methods and Tools,2006

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