Scalable benchmark synthesis for performance evaluation of NoC core mapping-Reference-Cited by-同舟云学术

Scalable benchmark synthesis for performance evaluation of NoC core mapping

Published:2020-11 Issue: Volume:79 Page:103272
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Kumar Aruru Sai,Rao T.V.K. Hanumantha

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference47 articles.

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4. Energy and Performance Evaluation of a Dimension Order Routing Algorithm For Mesh of Tree-based Network-On-Chip Architecture;Manna,2010

5. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks;Kim,2006

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