Scalable benchmark synthesis for performance evaluation of NoC core mapping

Author:

Kumar Aruru Sai,Rao T.V.K. Hanumantha

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference47 articles.

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2. Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips;DiTomaso;IEEE Tran. Very Large Scale Integration Systems,2013

3. Virtual channels in networks on chip: implementation and evaluation on hermesNoC;Mello;18th Symposium on Integrated Circuits and Systems Design,2005

4. Energy and Performance Evaluation of a Dimension Order Routing Algorithm For Mesh of Tree-based Network-On-Chip Architecture;Manna,2010

5. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks;Kim,2006

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