An O(1) time complexity sorting network for small number of inputs with hardware implementation-Reference-Cited by-同舟云学术

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An O(1) time complexity sorting network for small number of inputs with hardware implementation

Published:2020-09 Issue: Volume:77 Page:103203
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Jelodari Parham Taghinia,Kordasiabi Mojtaba Parsa,Sheikhaei Samad,Forouzandeh Behjat

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference28 articles.

1. FPGA-based implementation of sorting networks in MMC applications;Ricco;18th Eur. Conf. Power Electron. Appl. IEEE,2016

2. Parallel multiplication using fast sorting networks;Fiore;IEEE Trans. Comput.,1999

3. Low power design essentials;Rabaey;Springer Sci. Bus. Media,2009

4. A new internal sorting method,” goodyear aerospace corporation;Batcher;Rep. No. GER-11,1964

5. A sorting problem;Bose;J. ACM (JACM),1962

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2. Two Rank Sorting for Successive Cancellation List Decoding of Polar Codes;IECON 2022 – 48th Annual Conference of the IEEE Industrial Electronics Society;2022-10-17

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