Evaluation of low power consumption network on chip routing architecture-Reference-Cited by-同舟云学术

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Evaluation of low power consumption network on chip routing architecture

Published:2021-04 Issue: Volume:82 Page:103809
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

T S Arulananth,M Baskar,S M Udhaya Sankar,Thiagarajan R.,G Arul Dalton,Rajeshwari Pasupuleti Raja,Kumar Aruru Sai,A Suresh

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference35 articles.

1. Achieving high-performance on-chip networks with shared buffer Routers;Tran;IEEE Trans. Very Large Scale Integration (VLSI) Syst.,2014

2. Networks on chip: A new paradigm for systems on chip design;Benini;IEEE Comp.,2001

3. PCA Based Dimensional Data Reduction and Segmentation for DICOM Images;Arulananth;Neural Process Lett.,2020

4. Invariant packet feature with network conditions for efficient low rate attack detection in multimedia networks for improved QoS;Suchithra;J. Ambient Intell. Human Comput.,2020

5. Power punch: Towards non-blocking power-gating of noc routers;Chen,2015

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4. A deep learning based latency aware predictive routing model for network‐on‐chip architectures;International Journal of Communication Systems;2023-09-07

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