L3: An FPGA-based multilayer maze routing accelerator

Author:

Nestor John A.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference24 articles.

1. An Introduction to VLSI Physical Design;Sarrafzadeh,1996

2. Algorithms for VLSI Physical Design Automation;Sherwani,1999

3. An Algorithm for Path Connections and its Applications;Lee;IRE Transactions on Electronic Computers,1961

4. Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing;Batterywala,2002

5. A Hardware router;Breuer;Journal of Digital Systems,1981

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Congestion-based Routing Model and Its Optimization Method for VLSI Routing;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2018-11-07

2. Verilog HDL Simulator Technology: A Survey;Journal of Electronic Testing;2014-05-23

3. A comparison of hardware acceleration methods for VLSI Maze routing;2009 IEEE Toronto International Conference Science and Technology for Humanity (TIC-STH);2009-09

4. L4: An FPGA-Based Accelerator for Detailed Maze Routing;2007 International Conference on Field Programmable Logic and Applications;2007-08

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