A two stage pipeline architecture for hardware implementation of multi-level decomposition of 1-D framelet transform-Reference-Cited by-同舟云学术

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A two stage pipeline architecture for hardware implementation of multi-level decomposition of 1-D framelet transform

Published:2024-07 Issue: Volume:108 Page:105064
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Kumar Kasetty Praveen^ORCID,Kanhe Aniruddha

Publisher

Elsevier BV

Reference31 articles.

1. Wavelets and Subband Coding;Vetterli,1995

2. Wavelet Transforms and Their Applications;Debnath,2002

3. Framelets and Wavelets: Algorithms, Analysis, and Applications;Han,2018

4. The dual-tree complex wavelet transform;Selesnick;IEEE Signal Process. Mag.,2005

5. A theory for multiresolution signal decomposition: the wavelet representation;Mallat;IEEE Trans. Pattern Anal. Mach. Intell.,1989

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