Efficient dual-precision floating-point fused-multiply-add architecture-Reference-Cited by-同舟云学术

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Efficient dual-precision floating-point fused-multiply-add architecture

Published:2018-03 Issue: Volume:57 Page:23-31
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Arunachalam V.,Joseph Raj Alex Noel,Hampannavar Naveen,Bidul C.B.

Funder

School of Electrical Engineering, VIT University, Vellore

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference21 articles.

1. Design of the IBM RISC System/6000 floating-point execution unit;Montoye;IBM J. Res. Dev.,1990

2. Second-generation RISC floating point with multiply-add fused;Hokenek;IEEE J. Solid-State Circuits,1990

3. The vector floating-point unit in a synergistic processor element of a cell processor;Mueller,2005

4. Cell broadband engine architecture and its first implementation – a performance view;Chen;IBM J. Res. Dev.,2007

5. The IBM Blue Gene/Q Compute hip;Haring;IEEE Micro,2012

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2. All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation;Applied Sciences;2023-03-23

3. FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit;Microprocessors and Microsystems;2023-03

4. Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02

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