Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor-Reference-Cited by-同舟云学术

Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor

Published:2009-06 Issue:4 Volume:33 Page:290-294
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Berekovic Mladen,Kanstein Andreas,Mei Bingfeng,Sutter Bjorn De

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference15 articles.

1. A 600MHz VLIW–DSP;Agarwala;IEEE Journal of Solid-State Circuits,2002

2. Scalable processor instruction set extension;Becker;IEEE Design and Test of Computers,2005

3. P.P. Chang, S.A. Mahlke, W.Y. Chen, N.J. Warter, W.-M. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, in: Proceedings of the 18th International Symposium on Computer Architecture (ISCA), 1991, pp. 266–275.

4. R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, in: Proceedings of Design, Automation and Test in Europe (DATE), 2001, pp. 642–649.

5. ISO/IEC 13818-1/-2/-3, Information Technology—Generic Coding of Moving Pictures and Associated Audio: Systems/Video/Audio, 1996.

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture;Tsinghua Science and Technology;2021-10

2. Coarse-Grained Reconfigurable Array Architectures;Handbook of Signal Processing Systems;2018-10-14

3. BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-07

4. Coarse-Grained Reconfigurable Array Architectures;Handbook of Signal Processing Systems;2013

5. Background and Related Works;3D Video Coding for Embedded Devices;2013