Efficient and high performance FPGA-based rectification architecture for stereo vision-Reference-Cited by-同舟云学术

Efficient and high performance FPGA-based rectification architecture for stereo vision

Published:2013-11 Issue:8 Volume:37 Page:1144-1154
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Zicari Paolo

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference27 articles.

1. J.I. Woodfill, G. Gordon, R. Buck, Tyzx DeepSea high speed stereo vision system, in: Conference on Computer Vision and Pattern Recognition Workshop, 2004, CVPRW ’04, 27–02 June 2004, pp. 41.

2. J.I. Woodfill, G. Gordon, D. Jurasek, T. Brown, R. Buck, The Tyzx DeepSea G2 vision system, ATaskable, embedded stereo camera, in: Conference on Computer Vision and Pattern Recognition Workshop, 2006, CVPRW ’06, 17–22 June 2006, pp. 126.

3. D.K. Masrani, W.J. MacLean, A real-time large disparity range stereo-system using FPGAs, in: IEEE International Conference on Computer Vision Systems, 2006 ICVS ‘06, 04–07 January 2006, pp. 13.

4. A. Darabiha, J. Rose, J.W. Maclean, Video-rate stereo depth measurement on programmable hardware, in: Proceedings 2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 2003, vol. 1, 18–20 June 2003, pp. I-203–I-210.

5. K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger, Hardware implementation of an SAD based stereo vision algorithm, in: IEEE Conference on Computer Vision and Pattern Recognition, 2007, CVPR ’07, 17–22 June 2007, pp. 1–6.

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